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| capsense ? applications cy8c20x36a/46a/66a/96a cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-54459 rev. ** revised july 14, 2009 features 1.71v to 5.5v operating range low power capsense? block ? configurable capacitive sensing elements ? supports combination of capsense buttons, sliders, touch- pads, touch screens, and proximity sensor powerful harvard architecture processor ? m8c processor speeds running to 24 mhz ? low power at high speed ? interrupt controller ? temperature range: -40c to +85c flexible on-chip memory ? three program/data storage size options: ? cy8c20x36a: 8k flash / 1k sram ? cy8c20x46a, cy8c20x96a: 16k flash / 2k sram ? cy8c20x66a: 32k flash / 2k sram ? 50,000 flash erase/write cycles ? partial flash updates ? flexible protection modes ? in-system serial programming (issp) full speed usb ? available on cy8c20646a, cy8c20666a, cy8c20x96a only ? 12 mbps usb 2.0 compliant ? eight unidirectional endpoints ? one bidirectional control endpoint ? dedicated 512 byte buffer ? internally regulated at 3.3v precision, programmable clocking ? internal main oscillator: 6/12/24 mhz 5% ? internal low speed oscillator at 32 khz for watchdog and sleep timers ? precision 32 khz oscillator for optional external crystal ? 0.25% accuracy for usb with no external components (cy8c20646a, cy8c20666a, cy8c20x96a only) programmable pin configurations ? up to 36 gpio (depending on package) ? dual mode gpio: all gpio support digital i/o and analog input ? 25 ma sink current on all gpio ? pull up, high z, open drain modes on all gpio ? cmos drive mode (5 ma source current) on ports 0 and 1: ? 20 ma (at 3.0v) total source current on port 0 ? 20 ma (at 3.0v) total source current on port 1 ? selectable, regulated digital i/o on port 1 ? configurable input threshold on port 1 ? hot swap capability on all port 1 gpio versatile analog mux ? common internal analog bus ? simultaneous connection of i/o ? high psrr comparator ? low dropout voltage regulator for all analog resources additional system resources ? i2c slave: ? selectable to 50 khz, 100 khz, or 400 khz ? no clock stretching required (under most conditions) ? implementation during sleep modes with less than 100 a ? hardware address validation ? spi? master and slave: configurable 46.9 khz to 12 mhz ? three 16-bit timers ? watchdog and sleep timers ? internal voltage reference ? integrated supervisory circuit ? 8-bit delta-sigma analog-to-digital converter ? two general purpose high speed, low power analog com- parators complete development tools ? free development tool (psoc designer?) ? full featured, in-circuit emulator and programmer ? full speed emulation ? complex breakpoint structure ? 128k trace memory package options ? cy8c20x36a: ? 16-pin 3 x 3 x 0.6 mm qfn ? 24-pin 4 x 4 x 0.6 mm qfn ? 32-pin 5 x 5 x 0.6 mm qfn ? 48-pin ssop ? 48-pin 7 x 7 x 1.0 mm qfn ? cy8c20x46a: ? 16-pin 3 x 3 x 0.6 mm qfn ? 24-pin 4 x 4 x 0.6 mm qfn ? 32-pin 5 x 5 x 0.6 mm qfn ? 48-pin ssop ? 48-pin 7 x 7 x 1.0 mm qfn (with usb) ? cy8c20x96a: ? 24-pin 4 x 4 x 0.6 mm qfn (with usb) ? 32-pin 5 x 5 x 0.6 mm qfn (with usb) ? cy8c20x66a: ? 32-pin 5 x 5 x 0.6 mm qfn ? 48-pin 7 x 7 x 1.0 mm qfn (with usb) ? 48-pin ssop [+] feedback
cy8c20x36a/46a/66a/96a document number: 001-54459 rev. ** page 2 of 38 logic block diagram capsense system 1k/2k sram interrupt controller sleep and watchdog multiple clock sources internal low speed oscillator (ilo) 6/12/24 mhz internal main oscillator (imo) psoc core cpu core (m8c) supervisory rom (srom) 8k/16k/32k flash nonvolatile memory system resources system bus analog reference system bus port 3 port 2 port 1 port 0 capsense module global analog interconnect 1.8/2.5/3v ldo analog mux two comparators i2c slave spi master/ slave por and lvd usb system resets internal voltage references three 16-bit programmable timers pwrsys (regulator) port 4 digital clocks [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. ** page 3 of 38 psoc ? functional overview the psoc family consists of on-chip controller devices. these devices are designed to replace multiple traditional mcu-based components with one, low cost single-chip programmable component. a psoc device includes configurable analog and digital blocks, and programmable interconnect. this architecture allows the user to create cust omized peripheral configurations, to match the requirements of each individual application. additionally, a fast cpu, flash program memory, sram data memory, and configurable i/o are included in a range of convenient pinouts. the architecture for this device family, as shown in the logic block diagram on page 2 , is comprised of three main areas: the core, the capsense analog syst em, and the system resources (including a full speed usb port). a common, versatile bus allows connection between i/o and the analog system. each cy8c20x36a/46a/66a/96a psoc device includes a dedicated capsense block that provides sensing and scanning control circuitry for capacitive sensing applications. depending on the psoc package, up to 36 general purpose io (gpio) are also included. the gpio provides access to the mcu and analog mux. psoc core the psoc core is a powerful engine that supports a rich instruction set. it encompasses sram for data storage, an interrupt controller, sleep and watchdog timers, and imo (internal main oscillator) and ilo (internal low speed oscillator). the cpu core, called the m8c, is a powerful processor with speeds up to 24 mhz. the m8c is a 4-mips, 8-bit harvard archi- tecture microprocessor. system resources provide additional capability, such as configurable usb and i2c slave/spi master-slave communication interface, three 16-bit programmable timers, and various system resets supported by the m8c. the analog system is composed of the capsense psoc block and an internal 1.2v analog re ference, which together support capacitive sensing of up to 36 inputs. capsense analog system the analog system contains the capacitive sensing hardware. several hardware algorithms are supported. this hardware performs capacitive sensing and scanning without requiring external components. capacitive sensing is configurable on each gpio pin. scanning of enabled capsense pins are completed quickly and easily across multiple ports. figure 1. analog system block diagram analog multiplexer system the analog mux bus can connect to every gpio pin. pins are connected to the bus individually or in any combination. the bus also connects to the analog system for analysis with the capsense block comparator. switch control logic enables selected pins to precharge continuously under hardware control. this enables capacitive measurement for applications su ch as touch sensing. other multiplexer applications include: complex capacitive sensing inte rfaces, such as sliders and touchpads. chip-wide mux that allows analog input from any i/o pin. crosspoint connection between any i/o pin combinations. when designing capacitive sensing applications, refer to the latest signal-to-noise signal level requirements application notes, which can be found under http://www.cypress.com > documentation > application notes. in general, and unless otherwise noted in the relevant application notes, the minimum signal-to-noise ratio (snr) for capsense applications is 5:1. idac reference buffer vr cinternal analog global bus cap sense counters comparator mux mux refs capsense clock select oscillator csclk imo [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. ** page 4 of 38 additional system resources system resources, some of which are listed in the previous sections, provide additional capability useful to complete systems. additional resources in clude low voltage detection and power on reset. the merits of each system resource are listed here: the i2c slave/spi master-slave module provides 50/100/400 khz communication over two wires. spi communication over three or four wires r uns at speeds of 46.9 khz to 3 mhz (lower for a slower system clock). the i2c hardware address recognition feature reduces the already low power consumption by eliminating the need for cpu intervention until a packet addressed to the target device is received. low voltage detection (lvd) interrupts can signal the application of falling voltage levels, while the advanced por (power-on-reset) circuit elim inates the need for a system supervisor. an internal reference provides an absolute reference for capac- itive sensing. a register-controlled bypass mode allows the user to disable the ldo. standard cypress psoc ide tools are available for debugging the cy8c20x36a/46a/66a/96a fam ily of parts. however, the additional trace length and a minimal ground plane in the flex- pod can create noise problems that make it difficult to debug the design. a custom bonded on-chip debug (ocd) device is available in an 48-pin qfn package. the ocd device is recommended for debugging desi gns that have high current and/or high analog accuracy requirements. the qfn package is compact and is connected to the ice through a high density connector. getting started the quickest way to understand psoc silicon is to read this data sheet and then use the psoc designer integrated development environment (ide). this data sh eet is an overview of the psoc integrated circuit and presents specific pin, register, and electrical specifications. for in depth information, along with detailed programming details, see the psoc ? programmable system-on-chip? technical reference manual for cy8c20x36a/46a/66a/96a psoc devices. for up-to-date ordering, packaging, and electrical specification information, see the latest pso c device data sheets on the web at www.cypress.com/psoc . application notes application notes are an excellent introduction to the wide variety of possible psoc designs. they are located here: www.cypress.com/psoc . select application notes under the documentation tab. development kits psoc development kits are available online from cypress at www.cypress.com/shop and through a growing number of regional and global distributors, which include arrow, avnet, digi- key, farnell, future electronics, and newark. training free psoc technical traini ng (on demand, webinars, and workshops) is available online at www.cypress.com/training . the training covers a wide variety of topics and skill levels to assist you in your designs. cypros consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant go to www.cypress.com/cypros . solutions library visit our growing library of solution focused designs at www.cypress.com/solutions . here you can find various application designs that include firmware and hardware design files that enable yo u to complete your designs quickly. technical support for assistance with technical issues, search knowledgebase articles and forums at www.cypress.com/support . if you cannot find an answer to your question, call technical support at 1-800- 541-4736. [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. ** page 5 of 38 development tools psoc designer is a microsoft ? windows-based, integrated development environment for the programmable system-on- chip (psoc) devices. the psoc designer ide and application runs on windows xp and windows vista. this system provides design database management by project, an integrated debugger with in -circuit emulator, in-system programming support, and built-i n support for third-party assem- blers and c compilers. psoc designer also supports c language compilers developed specifically for the devices in the psoc family. psoc designer software subsystems system-level view the system-level view is a drag-and-drop visual embedded system design environment based on psoc express. in this view you solve design problems the same way you might think about the system. select input and output devices based upon system requirements. add a comm unication interface and define the interface to the system (reg isters). define when and how an output device changes state based upon any/all other system devices. based upon the design , psoc designer automatically selects one or more psoc dev ices that match your system requirements. psoc designer generates all embedded code, then compiles and links it into a programming file for a specific psoc device. chip-level view the chip-level view is a more traditional integrated development environment (ide) based on psoc designer 4.x. you choose a base device to work with and then select different onboard analog and digital components called user modules that use the psoc blocks. examples of user modules are adcs, dacs, amplifiers, and filters. you conf igure the user modules for your chosen application and connect them to each other and to the proper pins. then you generate your project. this prepopulates your project with apis and libraries that you can use to program your application. the tool also supports easy deve lopment of multiple configura- tions and dynamic reconfigurat ion. dynamic reconfiguration allows for changing configurations at run time. hybrid designs you can begin in the system-level view, allow it to choose and configure your user modules, routing, and generate code, then switch to the chip-level view to gain complete control over on- chip resources. all views of the project share common code editor, builder, and common deb ug, emulation, and programming tools. code generation tools psoc designer supports multiple third-party c compilers and assemblers. the code generation tools work seamlessly within the psoc designer interface and have been tested with a full range of debugging tools. the choice is yours. assemblers. the assemblers allow assembly code to be merged seamlessly with c code. link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. c language compilers. c language compilers are available that support the psoc family of devices. the products allow you to create complete c programs for the psoc family devices. the optimizing c compilers provide all the features of c tailored to the psoc architecture. they come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger psoc designer has a debug environment that provides hardware in-circuit emulation, al lowing you to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow the designer to read and program and read and write data memory, read and write i/o registers, read and write cpu r egisters, set and clear break- points, and provide program run, halt, and step control. the debugger also allows the designer to create a trace buffer of registers and memory lo cations of interest. online help system the online help system displays on line, context-sensitive help for the user. designed for procedural and quick reference, each functional subsystem has its ow n context-sensitive help. this system also provides tutorials an d links to faqs and an online support forum to aid the designer in getting started. in-circuit emulator a low cost, high functionality in-circuit emulator (ice) is available for development support. this hardware has the capability to progra m single devices. the emulator consists of a base unit that connects to the pc by way of a usb port. the base unit is universal and operates with all psoc devices. emulation p ods for each device family are available separately. the emulation pod takes the place of the psoc device in the target board and performs full speed (24 mhz) operation. [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. ** page 6 of 38 designing with psoc designer the development process for the psoc device differs from that of a traditional fixed function microprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays divi dends in managing specification change during development and by lowering inventory costs. these configurable resources, called psoc blocks, have the ability to implement a wide variet y of user-selectable functions. the psoc development process can be summarized in the following four steps: 1. select components 2. configure components 3. organize and connect 4. generate, verify, and debug select components both the system-level and chip-l evel views provide a library of pre-built, pre-tested hardware peripheral components. in the system-level view these com ponents are called ?drivers? and correspond to inputs (a thermistor, for example), outputs (a brushless dc fan, for example) , communication interfaces (i 2 c- bus, for example), and the logic to control how they interact with one another (called valuators). in the chip-level view the components are called ?user modules.? user modules make selecting and implementing peripheral devices simple, and come in analog, digital, and programmable system-on-chip varieties. configure components each of the components you select establishes the basic register settings that implement the selected function. they also provide parameters and properties that allow you to tailor their precise configuration to your particular application. for example, a pulse width modulator (pwm) user module configures one or more digital psoc blocks, one for each 8 bits of resolution. the user module parameters permit you to establish the pulse width and duty cycle. configure the parameters and properties to corre- spond to your chosen application. enter values directly or by selecting values from drop-down menus. both the system-level drivers an d chip-level user modules are documented in data sheets that are viewed directly in psoc designer. these data sheets explain the internal operation of the component and provide performance specifications. each data sheet describes the use of each user module parameter or driver property, and other information you may need to successfully implement your design. organize and connect you build signal chains at the chip level by interconnecting user modules to each other and the i/o pins, or connect system-level inputs, outputs, and communication interfaces to each other with valuator functions. in the system-level view select ing a potentiometer driver to control a variable speed fan driver and setting up the valuators to control the fan speed based on input from the pot selects, places, routes, and configures a programmable gain amplifier (pga) to buffer the input from the potentiometer, an analog-to- digital converter (adc) to conver t the potentiometer?s output to a digital signal, and a pwm to control the fan. in the chip-level view, you perform the selection, configuration, and routing so that you have comp lete control over the use of all on-chip resources. generate, verify, and debug when you are ready to test the hardware configuration or move on to developing code for the project, you perform the ?generate configuration files? step. this causes psoc designer to generate source code that automat ically configures the device to your specification a nd provides the software for the system. both system-level and chip-lev el designs generate software based on your design. the chip-level design provides application programming interfaces (apis) with high-level functions to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed. the system-level design also generates a c ma in() program that completely controls the chosen application and contains placeholders for custom code at strategic positions allowing you to further refine the software without disrupting the generated code. a complete code development environment allows you to develop and customize your applications in c, assembly language, or both. the last step in the development process takes place inside psoc designer?s debugger (access by clicking the connect icon). psoc designer downloads the hex image to the ice where it runs at full speed. psoc designer debugging capabil- ities rival those of systems costing many times more. in addition to traditional single-step, run-to-breakpoint and watch-variable features, the debug interface provides a large trace buffer and allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. ** page 7 of 38 document conventions acronyms used the following table lists the acronyms that are used in this document. units of measure a units of measure table is locat ed in the electrical specifications section. table 11 on page 17 lists all the abbreviations used to measure the psoc devices. numeric naming hexadecimal numbers are represented with all letters in uppercase with an appended lowercas e ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? prefix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). numbers not indicat ed by an ?h?, ?b?, or 0x are decimal. table 1. acronyms acronym description ac alternating current api application programming interface cpu central processing unit dc direct current fsr full scale range gpio general purpose i/o gui graphical user interface ice in-circuit emulator ilo internal low speed oscillator imo internal main oscillator i/o input/output lsb least-significant bit lvd low voltage detect msb most-significant bit por power on reset ppor precision power on reset psoc? programmable system-on-chip? slimo slow imo sram static random access memory [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. ** page 8 of 38 pinouts the cy8c20x36a/46a/66a/96a psoc device is available in a variet y of packages which are listed and illustrated in the following tables. every port pin (labeled with a ?p?) is capable of digital i/o and connection to the common analog bus. however, vss, vd d, and xres are not capable of digital i/o. 16-pin qfn (no e-pad) table 2. pin definitions - CY8C20236A, cy8c20246a psoc device [2] pin no. type name description figure 2. CY8C20236A, cy8c20246a psoc device digital analog 1 i/o i p2[5] crystal output (xout) 2 i/o i p2[3] crystal input (xin) 3 iohr i p1[7] i2c scl, spi ss 4 iohr i p1[5] i2c sda, spi miso 5 iohr i p1[3] spi clk 6 iohr i p1[1] issp clk [1] , i2c scl, spi mosi 7 power vss ground connection 8 iohr i p1[0] issp data [1] , i2c sda, spi clk 9 iohr i p1[2] 10 iohr i p1[4] optional external clock (extclk) 11 input xres active high external reset with internal pull down 12 ioh i p0[4] 13 power vdd supply voltage 14 ioh i p0[7] 15 ioh i p0[3] integrating input 16 ioh i p0[1] integrating input legend a = analog, i = input, o = output, oh = 5 ma high output drive, r = regulated output. qfn (top view) ai, xout, p2[5] ai, i2c scl, spi ss, p1[7] ai, i2c sda, spi miso, p1[5] ai, spi clk, p1[3] 1 2 3 4 11 10 9 16 15 14 13 p0[3], ai p0[7], ai vdd p0[4], ai ai, clk 1 , spi mosi, p1[1] ai, data 1 , i2c sda, spi clk, p1[0] p1[2], ai ai, xin, p2[3] p1[4], extclk, ai xres p0[1], ai vss 12 5 6 7 8 notes 1. these are the issp pins, which are not high z at por (power on reset). 2. during power up or reset event, device p1[1] and p1[0] may dist urb the i2c bus. use alternate pins if you encounter any issue s. [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. ** page 9 of 38 24-pin qfn note 3. the center pad (cp) on the qfn package must be connected to gr ound (vss) for best mechanical, thermal, and electrical perform ance. if not connected to ground, it must be electrically floated and not connected to any other signal. table 3. pin definitions - cy8c20336a, cy8c20346a [2, 3] pin no. type name description figure 3. cy8c20336a, cy8c20346a psoc device digital analog 1 i/o i p2[5] crystal output (xout) 2 i/o i p2[3] crystal input (xin) 3 i/o i p2[1] 4 iohr i p1[7] i2c scl, spi ss 5 iohr i p1[5] i2c sda, spi miso 6 iohr i p1[3] spi clk 7 iohr i p1[1] issp clk [1] , i2c scl, spi mosi 8 nc no connection 9 power vss ground connection 10 iohr i p1[0] issp data [1] , i2c sda, spi clk 11 iohr i p1[2] 12 iohr i p1[4] optional external clock input (extclk) 13 iohr i p1[6] 14 input xres active high external reset with internal pull down 15 i/o i p2[0] 16 ioh i p0[0] 17 ioh i p0[2] 18 ioh i p0[4] 19 ioh i p0[6] 20 power vdd supply voltage 21 ioh i p0[7] 22 ioh i p0[5] 23 ioh i p0[3] integrating input 24 ioh i p0[1] integrating input cp power vss center pad must be connected to ground legend a = analog, i = input, o = output, oh = 5 ma high output drive, r = regulated output. ai, data 2 , i2c sda, spi clk, p1[0] qfn (top view) ai, i2c scl, spi ss, p1[7] ai, i2c sda, spi miso, p1[5] ai, spi clk, p1[3] 1 2 3 4 5 6 18 17 16 15 14 13 p0[2], ai p0[0], ai 24 23 22 21 20 19 p0[3], ai p0[5], ai p0[7], ai vdd p0[4], ai 7 8 9 10 11 12 spi mosi, p1[1] ai, p1[2] ai, p2[1] nc p1[6], ai ai, extclk, p1[4] xres p2[0], ai p0[6], ai ai, clk 2 , i2c scl p0[1], ai vss ai, xout, p2[5] ai, xin, p2[3] [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. ** page 10 of 38 24-pin qfn with usb table 4. pin definitions - cy8c20396a psoc device [2, 3] pin no. type name description digital analog 1 i/o i p2[5] 2 i/o i p2[3] 3 i/o i p2[1] 4 iohr i p1[7] i2c scl, spi ss 5 iohr i p1[5] i2c sda, spi miso 6 iohr i p1[3] spi clk 7 iohr i p1[1] issp clk, i2c scl, spi mosi 8 power vss ground 9 i/o i d+ usb d+ 10 i/o i d- usb d- 11 power vdd supply 12 iohr i p1[0] issp data, i2c sda 13 iohr i p1[2] 14 iohr i p1[4] optional external clock input (extclk) 15 iohr i p1[6] 16 reset input xres active high external reset with internal pull down 17 ioh i p0[0] 18 ioh i p0[2] 19 ioh i p0[4] 20 ioh i p0[6] 21 ioh i p0[7] 22 ioh i p0[5] 23 ioh i p0[3] integrating input 24 ioh i p0[1] integrating input cp power vss thermal pad must be connected to ground legend i = input, o = output, oh = 5 ma high output drive, r = regulated output p0[7] i2 c sda, spi miso, p1[5] d- qfn ( top view ) i2 c scl, spi ss, p1[7] spi clk, p1[3] 1 2 3 4 5 6 18 17 16 15 14 13 p0[0] xres 24 23 22 21 20 19 p0[3] p0[5] p0[6] p0[2] 7 8 9 10 11 12 issp clk, i2c scl, spi mosi, p1[1] vdd p2[1] vss p1[2] issp data, i2c sda, p1[0] p1[4] , extclk p1[6] p0[4] p0[1], ai d+ p2[5] p2[3] figure 4. cy8c20396a psoc device [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. ** page 11 of 38 32-pin qfn table 5. pin definitions - cy8c20436a, cy8c20446a, cy8c20466a psoc device [2, 3] pin no. type name description figure 5. cy8c20436a, cy8c20446a, cy8c20466a psoc device digital analog 1 ioh i p0[1] integrating input 2 i/o i p2[7] 3 i/o i p2[5] crystal output (xout) 4 i/o i p2[3] crystal input (xin) 5 i/o i p2[1] 6 i/o i p3[3] 7 i/o i p3[1] 8 iohr i p1[7] i2c scl, spi ss 9 iohr i p1[5] i2c sda, spi miso 10 iohr i p1[3] spi clk. 11 iohr i p1[1] issp clk [1] , i2c scl, spi mosi. 12 power vss ground connection. 13 iohr i p1[0] issp data [1] , i2c sda., spi clk 14 iohr i p1[2] 15 iohr i p1[4] optional external clock input (extclk) 16 iohr i p1[6] 17 input xres active high external reset with internal pull down 18 i/o i p3[0] 19 i/o i p3[2] 20 i/o i p2[0] 21 i/o i p2[2] 22 i/o i p2[4] 23 i/o i p2[6] 24 ioh i p0[0] 25 ioh i p0[2] 26 ioh i p0[4] 27 ioh i p0[6] 28 power vdd supply voltage 29 ioh i p0[7] 30 ioh i p0[5] 31 ioh i p0[3] integrating input 32 power vss ground connection cp power vss center pad must be connected to ground legend a = analog, i = input, o = output, oh = 5 ma high output drive, r = regulated output. ai, p0[1] ai, p2[7] ai, xout, p2[5] ai, xin, p2[3] ai, p2[1] ai, p3[3] qfn (top view) 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 vss p0 [3 ], ai p0 [7 ], ai vd d p0 [6 ], ai p0 [4 ], ai p0 [2 ], ai ai, p3[1] ai, i2c scl, spi ss, p1[7] p0[0], ai p2[6], ai p3[0], ai xres ai, i2c sda , sp i miso , p 1[5] ai, spi clk, p1[3] vss ai, p 1[2] ai, e xtclk , p 1[4] ai, p 1[6] p2[4], ai p2[2], ai p2[0], ai p3[2], ai p0 [5 ], ai ai, clk 4 , i2c scl, spi mosi, p1[1] ai, data 1 , i2c sda, spi clk, p1[0] [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. ** page 12 of 38 32-pin qfn (with usb) table 6. pin definitions - cy8c20496a psoc device [2, 3] pin no. type name description figure 5. cy8c20496a psoc device digital analog 1 ioh i p0[1] 2 i/o i p2[5] xtal out 3 i/o i p2[3] xtal in 4 i/o i p2[1] 5 iohr i p1[7] i2c scl, spi ss 6 iohr i p1[5] i2c sda, spi miso 7 iohr i p1[3] spi clk 8 iohr i p1[1] tc clk, i2c scl, spi mosi 9 power v ss ground pin 10 i i d+ usb phy 11 d- usb phy 12 power vdd power pin 13 iohr i p1[0] tc data*, i2c sda, spi clki 14 iohr i p1[2] 15 iohr i p1[4] extclk 16 iohr i p1[6] 17 input xres active high external reset with internal pull down 18 i/o i p3[0] 19 i/o i p3[2] 20 i/o i p2[0] 21 i/o i p2[2] 22 i/o i p2[4] 23 i/o i p2[6] 24 ioh i p0[0] 25 ioh i p0[2] 26 ioh i p0[4] 27 ioh i p0[6] 28 power vdd power pin 29 ioh i p0[7] 30 ioh i p0[5] 31 ioh i p0[3] 32 power vss ground pin legend a = analog, i = input, o = output, oh = 5 ma high output drive, r = regulated output. ai , p 0[ 1 ] xtal out , p 2 [ 5 ] xtal in , p2 [ 3 ] ai , p2 [ 1 ] i2c scl, spi ss , p 1[ 7] i2c sda, spi miso , p 1[ 5 ] qfn ( top view ) 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 vss p0 [3 ], ai p0 [7 ], ai vd d p0 [6 ], ai p0 [4 ], ai p0 [2 ], ai spi clk , p1 [3 ] tc clk, i2c scl, spi mosi,p1 [ 1 ] p0[0] , ai p2[6] , ai p3[0] , ai xres vss usb phy, d+ vdd ai, p 1[ 2] ai , e xt clk , p 1[ 4] ai, p 1[ 6] p2[4] , ai p2[2] , ai p2[0] , ai p3[2] , ai p0 [5 ], ai usb phy d- tc, dat a 1 , i2c sda, spi clk, p1[0] [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. ** page 13 of 38 48-pin ssop table 7. pin definitions - cy8c20536a, cy8c20546a, and cy8c20566a psoc device [2] pin no. digital analog name description figure 6. cy8c20536a, cy8c20546a, and cy8c20566a psoc device 1 ioh i p0[7] 2 ioh i p0[5] 3 ioh ip0[3] 4 ioh ip0[1] 5 i/o i p2[7] 6 i/o i p2[5] xtal out 7 i/o i p2[3] xtal in 8 i/o i p2[1] 9 nc no connection 10 nc no connection 11 i/o i p4[3] 12 i/o i p4[1] 13 nc no connection 14 i/o i p3[7] 15 i/o i p3[5] 16 i/o i p3[3] 17 i/o i p3[1] 18 nc no connection 19 nc no connection 20 iohr i p1[7] i2c scl, spi ss 21 iohr i p1[5] i2c sda, spi miso 22 iohr i p1[3] spi clk 23 iohr i p1[1] tc clk [1] , i2c scl, spi mosi 24 vss ground pin 25 iohr i p1[0] tc data [1] , i2c sda, spi clk 26 iohr i p1[2] 27 iohr i p1[4] ext clk 28 iohr ip1[6] 29 nc no connection 30 nc no connection 31 nc no connection 32 nc no connection pin no. digital analog name description 33 nc no connection 41 i/o i p2[2] 34 nc no connection 42 i/o i p2[4] 35 xres active high external reset with internal pull down 43 i/o i p2[6] 36 i/o i p3[0] 44 ioh i p0[0] 37 i/o i p3[2] 45 ioh i p0[2] 38 i/o i p3[4] 46 ioh i p0[4] 39 i/o i p3[6] 47 ioh i p0[6] 40 i/o i p2[0] 48 power vdd power pin legend a = analog, i = input, o = output, nc = no connection, h = 5 ma high output drive, r = regulated output option. ssop ai, p0[7] vdd ai, p0[5] p0[6], ai ai, p0[3] p0[4], ai ai p0[1] p0[2], ai ai, p2[7] p0[0], ai xtalout, p2[5] p2[6], ai xtalin, p2[3] p2[4], ai ai, p2[1] p2[2], ai nc p2[0], ai nc p3[6], ai ai, p4[3] p3[4], ai ai, p4[1] p3[2], ai nc p3[0], ai ai, p3[7] xres ai, p3[5] nc ai, p3[3] nc ai, p3[1] nc nc nc nc nc i2c scl, spi ss, p1[7] nc i2c sda, spi miso, p1[5] p1[6], ai spi clk, p1[3] p1[4], ext clk tc clk, i2c scl, spi mosi, p1[1] p1[2], ai vss p1[0], tc data, i2c sda, spi clk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 43 44 42 40 41 39 38 37 36 35 33 34 32 31 30 29 28 27 26 25 [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. ** page 14 of 38 48-pin qfn table 8. pin definitions - cy8c20636a psoc device [2, 3] pin no. digital analog name description figure 7. cy8c20636a psoc device 1 nc no connection 2 i/o i p2[7] 3 i/o i p2[5] crystal output (xout) 4 i/o i p2[3] crystal input (xin) 5 i/o i p2[1] 6 i/o i p4[3] 7 i/o ip4[1] 8 i/o i p3[7] 9 i/o i p3[5] 10 i/o i p3[3] 11 i/o i p3[1] 12 iohr i p1[7] i2c scl, spi ss 13 iohr i p1[5] i2c sda, spi miso 14 nc no connection 15 nc no connection 16 iohr i p1[3] spi clk 17 iohr i p1[1] issp clk [1] , i2c scl, spi mosi 18 power vss ground connection 19 dnu 20 dnu 21 power vdd supply voltage 22 iohr i p1[0] issp data [1] , i2c sda, spi clk 23 iohr i p1[2] 24 iohr i p1[4] optional external clock input (extclk) 25 iohr i p1[6] 26 input xres active high external reset with internal pull down 27 i/o i p3[0] 28 i/o ip3[2] 29 i/o ip3[4] pin no. digital analog name description 30 i/o ip3[6] 40 ioh i p0[6] 31 i/o i p4[0] 41 power vdd supply voltage 32 i/o i p4[2] 42 nc no connection 33 i/o i p2[0] 43 nc no connection 34 i/o i p2[2] 44 ioh i p0[7] 35 i/o i p2[4] 45 ioh i p0[5] 36 i/o i p2[6] 46 ioh i p0[3] integrating input 37 ioh i p0[0] 47 power vss ground connection 38 ioh i p0[2] 48 ioh i p0[1] 39 ioh i p0[4] cp power vss center pad must be connected to ground legend a = analog, i = input, o = output, nc = no connection h = 5 ma high output drive, r = regulated output. qfn (top view ) vss p0[3], ai p0[5 ], ai p0[7], ai vdd p0[6], ai p0[2], ai p0[0], ai 10 11 12 ai , p2[7] nc ai , xout, p2[5] ai, xin , p2[3] ai , p2[1] ai , p4[3] ai , p4[1] ai , p3[7] ai , p3[5] ai , p3[3] ai p 3[1] ai, i2 c scl, spi ss, p1[7] 35 34 33 32 31 30 29 28 27 26 25 36 48 47 4 6 45 44 43 42 41 4 0 39 38 37 p2[4] , ai p2[2] , ai p2[0] , ai p4[2] , ai p4[0] , ai p3[6] , ai p3[4] , ai p3[2] , ai p3[0 ], ai xres p1[6] , ai p2[6] , ai 1 2 3 4 5 6 7 8 9 13 14 15 16 17 18 19 20 21 22 23 24 i2c sda, spi miso, a i, p1[5] nc spiclk,ai,p1[3] ai, clk 6 , i2c scl, spi mosi, p1[1] vss dnu dnu vdd ai, data 1 ,i2csda,spiclk,p1[0] ai, p 1[2] ai, extclk, p1[4] nc nc nc p0[4], ai p0[1], ai [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. ** page 15 of 38 48-pin qfn with usb table 9. pin definitions - cy8c20646a, cy8c20666a psoc device [2, 3] pin no. digital analog name description figure 8. cy8c20646a, cy8c20666a psoc device 1 nc no connection 2 i/o i p2[7] 3 i/o i p2[5] crystal output (xout) 4 i/o i p2[3] crystal input (xin) 5 i/o i p2[1] 6 i/o i p4[3] 7 i/o ip4[1] 8 i/o i p3[7] 9 i/o i p3[5] 10 i/o i p3[3] 11 i/o i p3[1] 12 iohr i p1[7] i2c scl, spi ss 13 iohr i p1[5] i2c sda, spi miso 14 nc no connection 15 nc no connection 16 iohr i p1[3] spi clk 17 iohr i p1[1] issp clk [1] , i2c scl, spi mosi 18 power vss ground connection 19 i/o d+ usb d+ 20 i/o d- usb d- 21 power vdd supply voltage 22 iohr i p1[0] issp data [1] , i2c sda, spi clk 23 iohr i p1[2] 24 iohr i p1[4] optional external clock input (extclk) 25 iohr i p1[6] 26 input xres active high external reset with internal pull down 27 i/o i p3[0] 28 i/o ip3[2] 29 i/o ip3[4] pin no. digital analog name description 30 i/o ip3[6] 40 ioh i p0[6] 31 i/o i p4[0] 41 power vdd supply voltage 32 i/o i p4[2] 42 nc no connection 33 i/o i p2[0] 43 nc no connection 34 i/o i p2[2] 44 ioh i p0[7] 35 i/o i p2[4] 45 ioh i p0[5] 36 i/o i p2[6] 46 ioh i p0[3] integrating input 37 ioh i p0[0] 47 power vss ground connection 38 ioh i p0[2] 48 ioh i p0[1] 39 ioh i p0[4] cp power vss center pad must be connected to ground legend a = analog, i = input, o = output, nc = no connection h = 5 ma high output drive, r = regulated output. qfn (top view) vss p0[3], ai p0[5 ], ai p0[7], ai vdd p0[6], ai p0[2], ai p0[0], ai 10 11 12 ai , p2[7] nc ai, xout, p2[5] ai, xin , p2[3] ai , p2[1] ai, p4[3] ai, p4[1] ai, p3[7] ai, p3[5] ai, p3[3] ai, p3[1] ai, i2c scl, spi ss, p1[7] 35 34 33 32 31 30 29 28 27 26 25 36 48 47 46 45 44 43 42 41 40 39 38 37 p2[4], ai p2[2], ai p2[0], ai p4[2], ai p4[0], ai p3[6], ai p3[4], ai p3[2], ai p3[0 ], ai xres p1[6], ai p2[6], ai 1 2 3 4 5 6 7 8 9 13 14 15 16 17 18 19 20 21 22 23 24 i2c sda, spi miso, a i, p1[5] nc spi clk, a i, p1[3] ai, clk 6 , i2c scl, spi mosi, p1[1] vss d+ d- vdd ai, data 1 , i2c sda, spi clk, p1[0] ai, p1[2] ai, extclk, p1[4] nc nc nc p0[4], ai p0[1], ai [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. ** page 16 of 38 48-pin qfn ocd the 48-pin qfn part is for the cy8c20066a on-chip debug (ocd) psoc device. note that this part is only used for in-circuit debugging. [4] table 10. pin definitions - cy8c20066a psoc device [2, 3] pin no. digital analog name description figure 9. cy8c20066a psoc device 1 ocdoe ocd mode direction pin 2 i/o i p2[7] 3 i/o i p2[5] crystal output (xout) 4 i/o i p2[3] crystal input (xin) 5 i/o i p2[1] 6 i/o i p4[3] 7 i/o ip4[1] 8 i/o i p3[7] 9 i/o i p3[5] 10 i/o i p3[3] 11 i/o i p3[1] 12 iohr i p1[7] i2c scl, spi ss 13 iohr i p1[5] i2c sda, spi miso 14 cclk ocd cpu clock output 15 hclk ocd high speed clock output 16 iohr i p1[3] spi clk. 17 iohr i p1[1] issp clk [1] , i2c scl, spi mosi 18 power vss ground connection 19 i/o d+ usb d+ 20 i/o d- usb d- 21 power vdd supply voltage 22 iohr i p1[0] issp data (1) , i2c sda, spi clk 23 iohr i p1[2] pin no. digital analog name description 24 iohr i p1[4] optional external clock input (extclk) 37 ioh i p0[0] 25 iohr i p1[6] 38 ioh i p0[2] 26 input xres active high external reset with internal pull down 39 ioh i p0[4] 27 i/o i p3[0] 40 ioh i p0[6] 28 i/o ip3[2] 41 power vdd supply voltage 29 i/o ip3[4] 42 ocdo ocd even data i/o 30 i/o ip3[6] 43 ocde ocd odd data output 31 i/o i p4[0] 44 ioh i p0[7] 32 i/o i p4[2] 45 ioh i p0[5] 33 i/o i p2[0] 46 ioh i p0[3] integrating input 34 i/o i p2[2] 47 power vss ground connection 35 i/o i p2[4] 48 ioh i p0[1] 36 i/o i p2[6] cp power vss center pad must be connected to ground legend a = analog, i = input, o = output, nc = no connection h = 5 ma high output drive, r = regulated output. qfn (top view) vss p0[3], ai p0[5 ], ai p0[7], ai vdd p0[6], ai p0[2], ai p0[0], ai 10 11 12 a i , p2[7] ai, xout, p2[5] ai, xin , p2[3] ai , p2[1] ai , p4[3] ai , p4[1] ai, p3[7] ai, p3[5] ai, p3[3] ai, p3[1] ai, i2c scl, spi ss, p1[7] 35 34 33 32 31 30 29 28 27 26 25 36 48 47 46 45 44 43 42 41 40 39 38 37 p2[4], ai p2[2], ai p2[0], ai p4[2], ai p4[0], ai p3[6], ai p3[4], ai p3[2], ai p3[0], ai xres p1[6], ai p2[6], ai 1 2 3 4 5 6 7 8 9 13 14 15 16 17 18 19 20 21 22 23 24 i2c sda, spi miso, ai, p1[5] spi clk, a i, p1[3] ai, clk 6 , i2c scl, spi mosi, p1[1] vss d+ d- vdd ai, data 1 , i2c sda, spi clk, p1[0] ai, p1[2] ai, extclk, p1[4] p0[4], ai p0[1], ai ocdo e cclk hclk ocde ocdo note 4. this part is available in limited quantities for in-circuit debugging during prototype develop ment. it is not available in pr oduction volumes. [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. ** page 17 of 38 electrical specifications this section presents the dc and ac electr ical specifications of the cy8c20x36a/46a/66a/96a psoc devi ces. for the latest electr ical specifications, confirm that you have the most recent data sheet by visiting the web at http://www.cypress.com/psoc . f i g u r e 1 0 . vo l t a g e v e r s u s c p u f r e q u e n c y f i g u r e 11 . i m o f r e q u e n c y tr i m o p t i o n s the following table lists the units of me asure that are used in this section. table 11. units of measure symbol unit of measure symbol unit of measure c degree celsius ma milli-ampere db decibels ms milli-second ff femto farad mv milli-volts hz hertz na nanoampere kb 1024 bytes ns nanosecond kbit 1024 bits nv nanovolts khz kilohertz ohm ksps kilo samples per second pa picoampere k kilohm pf picofarad mhz megahertz pp peak-to-peak m megaohm ppm parts per million a microampere ps picosecond f microfarad sps samples per second h microhenry s sigma: one standard deviation s microsecond v volts w microwatts 5.5v 750 khz 24 mhz cpu frequency vdd voltage 5.5v 750 khz 6 mhz 24 mhz imo frequency vdd voltage 3 mhz 1.71v 1.71v 3 mhz v a l i d o p e r a t in g r e g i o n slimo mode = 01 12 mhz slimo mode = 00 slimo mode = 10 [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. ** page 18 of 38 absolute maximum ratings exceeding maximum ratings may shorten the useful li fe of the device. user guidelines are not tested. operating temperature table 12. absolute maximum ratings symbol description conditions min typ max units t stg storage temperature higher storage temperatures reduces data retention time. recommended storage temperature is +25c 25c. extended duration storage temperatures above 85 o c degrades reliability. ?55 +25 +125 c vdd supply voltage relative to vss ?0.5 ? +6.0 v v io dc input voltage vss ? 0.5 ? vdd + 0.5 v v ioz dc voltage applied to tri-state vss ?0.5 ? vdd + 0.5 v i mio maximum current into any port pin ?25 ? +50 ma esd electro static discharge voltage human body model esd 2000 ? ? v lu latch up current in accordance with jesd78 standard ? ? 200 ma table 13. operating temperature symbol description conditions min typ max units t a ambient temperature ?40 ? +85 c t j operational die temperature the temperature rise from ambient to junction is package specific. refer the table thermal impedances per package on page 34 . the user must limit the power consumption to comply with this requirement. ?40 ? +100 c [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. ** page 19 of 38 dc chip-level specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. dc general purpose io specifications the following tables list guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 3.0v to 5.5v an d ?40c t a 85c, 2.4v to 3.0v and ?40c t a 85c, or 1.71v to 2.4v and ?40c t a 85c, respectively. typical parameters apply to 5v and 3.3v at 25c and are for design guidance only. table 14. dc chip-level specifications symbol description conditions min typ max units vdd supply voltage refer the table dc por and lvd specifications on page 24 1.71 ? 5.5 v i dd24 supply current, imo = 24 mhz conditions are vdd = 3.0v, t a = 25c, cpu = 24 mhz. capsense running at 12 mhz, no i/o sourcing current ? 2.88 4.0 ma i dd12 supply current, imo = 12 mhz conditions are vdd = 3.0v, t a = 25c, cpu = 12 mhz. capsense running at 12 mhz, no i/o sourcing current ? 1.71 2.6 ma i dd6 supply current, imo = 6 mhz conditions are vdd = 3.0v, t a = 25c, cpu = 6 mhz. capsense running at 6 mhz, no i/o sourcing current ? 1.16 1.8 ma i sb0 deep sleep current vdd = 3.0v, t a = 25c, i/o regulator turned off ? 0.1 ? a i sb1 standby current with por, lvd and sleep timer vdd = 3.0v, t a = 25c, i/o regulator turned off ? 1.07 1.5 a table 15. 3.0v to 5.5v dc gpio specifications symbol description conditions min typ max units r pu pull up resistor 4 5.6 8 k v oh1 high output voltage port 2 or 3 pins ioh < 10 a, maximum of 10 ma source current in all ios vdd - 0.2 ? ? v v oh2 high output voltage port 2 or 3 pins ioh = 1 ma, maximum of 20 ma source current in all ios vdd - 0.9 ? ? v v oh3 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 ioh < 10 a, maximum of 10 ma source current in all ios vdd - 0.2 ? ? v v oh4 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 ioh = 5 ma, maximum of 20 ma source current in all ios vdd - 0.9 ? ? v v oh5 high output voltage port 1 pins with ldo regulator enabled for 3v out ioh < 10 a, vdd > 3.1v, maximum of 4 ios all sourcing 5 ma 2.85 3.00 3.3 v v oh6 high output voltage port 1 pins with ldo regulator enabled for 3v out ioh = 5 ma, vdd > 3.1v, maximum of 20 ma source current in all ios 2.20 ? ? v v oh7 high output voltage port 1 pins with ldo enabled for 2.5v out ioh < 10 a, vdd > 2.7v, maximum of 20 ma source current in all ios 2.35 2.50 2.75 v v oh8 high output voltage port 1 pins with ldo enabled for 2.5v out ioh = 2 ma, vdd > 2.7v, maximum of 20 ma source current in all ios 1.90 ? ? v v oh9 high output voltage port 1 pins with ldo enabled for 1.8v out ioh < 10 a, vdd > 2.7v, maximum of 20 ma source current in all ios 1.60 1.80 2.1 v [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. ** page 20 of 38 v oh10 high output voltage port 1 pins with ldo enabled for 1.8v out ioh = 1 ma, vdd > 2.7v, maximum of 20 ma source current in all ios 1.20 ? ? v v ol low output voltage iol = 25 ma, vdd > 3.3v, maximum of 60 ma sink current on even port pins (for example, p0[2] and p1[4]) and 60 ma sink current on odd port pins (for example, p0[3] and p1[5]) ??0.75v v il input low voltage ? ? 0.80 v v ih input high voltage 2.00 ? v v h input hysteresis voltage ? 80 ? mv i il input leakage (absolute value) ? 0.001 1 a c pin pin capacitance package and pin dependent te m p = 2 5 c 0.5 1.7 5 pf table 15. 3.0v to 5.5v dc gpio specifications (continued) symbol description conditions min typ max units [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. ** page 21 of 38 table 16. 2.4v to 3.0v dc gpio specifications symbol description conditions min typ max units r pu pull up resistor 4 5.6 8 k v oh1 high output voltage port 2 or 3 pins ioh < 10 a, maximum of 10 ma source current in all ios vdd - 0.2 ? ? v v oh2 high output voltage port 2 or 3 pins ioh = 0.2 ma, maxi mum of 10 ma source current in all ios vdd - 0.4 ? ? v v oh3 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 ioh < 10 a, maximum of 10 ma source current in all ios vdd - 0.2 ? ? v v oh4 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 ioh = 2 ma, maximum of 10 ma source current in all ios vdd - 0.5 ? ? v v oh5a high output voltage port 1 pins with ldo enabled for 1.8v out ioh < 10 a, vdd > 2.4v, maximum of 20 ma source current in all ios 1.50 1.80 2.1 v v oh6a high output voltage port 1 pins with ldo enabled for 1.8v out ioh = 1 ma, vdd > 2.4v, maximum of 20 ma source current in all ios 1.20 ? ? v v ol low output voltage iol = 10 ma, maximum of 30 ma sink current on even port pins (for example, p0[2] and p1[4]) and 30 ma sink current on odd port pins (for example, p0[3] and p1[5]) ? ? 0.75 v v il input low voltage ? ? 0.72 v v ih input high voltage 1.4 ? v v h input hysteresis voltage ? 80 ? mv i il input leakage (absolute value) ? 0.001 1 a c pin capacitive load on pins package and pin dependent te m p = 2 5 o c 0.5 1.7 5 pf table 17. 1.71v to 2.4v dc gpio specifications symbol description conditions min typ max units r pu pull up resistor 4 5.6 8 k v oh1 high output voltage port 2 or 3 pins ioh = 10 a, maximum of 10 ma source current in all i/os vdd - 0.2 ? ? v v oh2 high output voltage port 2 or 3 pins ioh = 0.5 ma, maximum of 10 ma source current in all i/os vdd - 0.5 ? ? v v oh3 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 ioh = 100 a, maximum of 10 ma source current in all i/os vdd - 0.2 ? ? v v oh4 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 ioh = 2 ma, maximum of 10 ma source current in all i/os vdd - 0.5 ? ? v v ol low output voltage iol = 5 ma, maximum of 20 ma sink current on even port pi ns (for example, p0[2] and p1[4]) and 30 ma sink current on odd port pins (for example, p0[3] and p1[5]) ??0.4v v il input low voltage ? ? 0.3 x vdd v v ih input high voltage 0.65 x vdd ? v [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. ** page 22 of 38 dc analog mux bus specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. dc low power comparat or specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. v h input hysteresis voltage ? 80 ? mv i il input leakage (absolute value) ? 0.001 1 a c pin capacitive load on pins package and pin dependent te m p = 2 5 o c 0.5 1.7 5 pf table 17. 1.71v to 2.4v dc gpio specifications (continued) symbol description conditions min typ max units table 18.dc characteristics ? usb interface symbol description conditions min typ max units rusbi usb d+ pull up resistance with idle bus 0.900 - 1.575 k rusba usb d+ pull up resistance while receiving traffic 1.425 - 3.090 k vohusb static output high 2.8 - 3.6 v volusb static output low -0.3v vdi differential input sensitivity 0.2 - v vcm differential input common mode range 0.8 - 2.5 v vse single ended receiver threshold 0.8 - 2.0 v cin transceiver capacitance - 50 pf iio hi-z state data line leakage on d+ or d- line -10 - +10 a rps2 ps/2 pull up resistance 3 5 7 k rext external usb series resistor in series with each usb pin 21.78 22.0 22.22 table 19. dc analog mux bus specifications symbol description conditions min typ max units r sw switch resistance to common analog bus ? ? 800 r gnd resistance of initialization switch to vss ? ? 800 the maximum pin voltage for measuring r sw and r gnd is 1.8v table 20. dc comparator specifications symbol description conditions min typ max units v lpc low power comparator (lpc) common mode maximum voltage limited to vdd 0.0 ? 1.8 v i lpc lpc supply current ? 10 40 a v oslpc lpc voltage offset ? 2.5 30 mv [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. ** page 23 of 38 comparator user module electrical specifications the following table lists the guaranteed maximum and minimum spec ifications. unless stated otherwis e, the specifications are fo r the entire device voltage and temperature operating range: ?40c <= ta <= 85c, 1.71v <= vdd <= 5.5v. adc electrical sp ecifications table 21. comparator user module electrical specifications symbol description conditions min typ max units t comp comparator response time 50 mv overdrive 70 100 ns offset 2.5 30 mv current average dc current, 50 mv overdrive 20 80 a psrr supply voltage >2v power supply rejection ratio 80 db supply voltage <2v power supply rejection ratio 40 db input range 0 1.5 v note 5. monotonicity is not guaranteed. table 22. adc user module electrical specifications symbol description conditions min typ max units input v in input voltage range this gives 72% of maximum code vss 1.3 v c in input capacitance 5pf res resolution settings 8, 9, or 10 8 10 bits s8 8-bit sample rate data clock set to 6 mhz. sample rate = 0.001/ (2^resolution/data clock) 23.4375 ksps s10 10-bit sample rate data clock set to 6 mhz. sample rate = 0.001/ (2^resolution/data clock) 5.859 ksps dc accuracy dnl [5] differential nonlinearity for any configuration -1 +2 lsb inl integral nonlinearity for any configuration -2 +2 lsb eoffset offset error 0 15 90 mv i adc operating current 275 350 a f clk data clock source is chip?s internal main oscillator. see device data sheet for accuracy. 2.25 12 mhz psrr power supply rejection ration psrr (vdd>3.0v) 24 db psrr (2.2 < vdd < 3.0) 30 db psrr (2.0 < vdd < 2.2) 12 db psrr (vdd < 2.0) 0 db egain gain error for any resolution 1 5 %fsr r in input resistance equivalent switched cap input resistance for 8-, 9-, or 10-bit resolution. 1/(500ff* data-clock) 1/(400ff* data-clock) 1/(300ff* data-clock) [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. ** page 24 of 38 dc por and lvd specifications the following table lists guaranteed maximum and minimum specif ications for the entire voltage and temperature ranges. dc programming specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 23. dc por and lvd specifications symbol description conditions min typ max units v ppor0 v ppor1 v ppor2 v ppor3 vdd value for ppor trip porlev[1:0] = 00b, hpor = 0 porlev[1:0] = 00b, hpor = 1 porlev[1:0] = 01b, hpor = 1 porlev[1:0] = 10b, hpor = 1 vdd must be greater than or equal to 1.71v during startup, reset from the xres pin, or reset from watchdog. 1.61 ? 1.66 2.36 2.60 2.82 1.71 2.41 2.66 2.95 v v v v v lvd0 v lvd1 v lvd2 v lvd3 v lvd4 v lvd5 v lvd6 v lvd7 vdd value for lvd trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.40 [6] 2.64 [7] 2.85 [8] 2.95 3.06 1.84 1.75 [9] 4.62 2.45 2.71 2.92 3.02 3.13 1.90 1.80 4.73 2.51 2.78 2.99 3.09 3.20 2.32 1.84 4.83 v v v v v v v v notes 6. always greater than 50 mv above v ppor1 voltage for falling supply. 7. always greater than 50 mv above v ppor2 voltage for falling supply. 8. always greater than 50 mv above v ppor3 voltage for falling supply. 9. always greater than 50 mv above v ppor0 voltage for falling supply. table 24. dc programming specifications symbol description conditions min typ max units vdd iwrite supply voltage for flash write operations 1.71 ? 5.25 v i ddp supply current during programming or verify ? 5 25 ma v ilp input low voltage during programming or verify see the appropriate dc general purpose io specifications on page 19 ? ? v il v v ihp input high voltage during programming or verify see appropriate dc general purpose io specifications on page 19 table on pages 15 or 16 v ih ? ? v i ilp input current when applying vilp to p1[0] or p1[1] during programming or verify driving internal pull down resistor ? ? 0.2 ma i ihp input current when applying vihp to p1[0] or p1[1] during programming or verify driving internal pull down resistor ? ? 1.5 ma v olp output low voltage during programming or verify ? ? vss + 0.75 v v ohp output high voltage during programming or verify see appropriate dc general purpose io specifications on page 19 table on page 16. for vdd > 3v use v oh4 in table 13 on page 18. v oh ? vdd v flash enpb flash write endurance erase/write cycles per block 50,000 ? ? - flash dr flash data retention following maximum flash write cycles; ambient temperature of 55c 10 20 ? years [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. ** page 25 of 38 ac chip-level specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 25. ac chip-level specifications symbol description conditions min typ max units f cpu cpu frequency 5.7 ? 25.2 mhz f 32k1 internal low speed oscillator frequency 19 32 50 khz f imo24 internal main oscillator frequency at 24 mhz setting 22.8 24 25.2 mhz f imo12 internal main oscillator frequency at 12 mhz setting 11.4 12 12.6 mhz f imo6 internal main oscillator frequency at 6 mhz setting 5.7 6.0 6.3 mhz dc imo duty cycle of imo 40 50 60 % t ramp supply ramp time 20 ? ? s t xrst external reset pulse width at power up after supply voltage is valid 1 ms t xrst2 external reset pulse width after power up [10] applies after part has booted 10 s note 10. the minimum required xres pulse length is longer when programming the device (see table 32 on page 28 ). [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. ** page 26 of 38 ac general purpose io specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. figure 12. gpio timing diagram table 26. ac gpio specifications symbol description conditions min typ max units f gpio gpio operating frequency normal strong mode port 0, 1 0 0 ? ? 6 mhz for 1.71v cy8c20x36a/46a/66a/96a document number: 001-54459 rev. ** page 28 of 38 ac programming specifications figure 13. ac waveform the following table lists the guaranteed maximum and minimum s pecifications for the entire vo ltage and temperature ranges. table 32. ac programming specifications symbol description conditions min typ max units t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data set up time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz t eraseb flash erase time (block) ? ? 18 ms t write flash block write time ? ? 25 ms t dsclk data out delay from falling edge of sclk 3.6 < vdd ? ? 60 ns t dsclk3 data out delay from falling edge of sclk 3.0 vdd 3.6 ? ? 85 ns t dsclk2 data out delay from falling edge of sclk 1.71 vdd 3.0 ? ? 130 ns t xrst3 external reset pulse width after power up required to enter programming mode when coming out of sleep 263 ? ? s sclk (p1[1]) t rsclk t fsclk sdata (p1[0]) t ssclk t hsclk t dsclk [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. ** page 29 of 38 ac i2c specifications the following table lists guaranteed maximum and minimum specif ications for the entire voltage and temperature ranges. figure 14. definition for timing for fast/standard mode on the i 2 c bus table 33. ac characteristics of the i2c sda and scl pins symbol description standard mode fast mode units min max min max f scli2c scl clock frequency 0 100 0 400 khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ? s t lowi2c low period of the scl clock 4.7 ?1.3 ? s t highi2c high period of the scl clock 4.0 ?0.6 ? s t sustai2c setup time for a repeated start condition 4.7 ?0.6 ? s t hddati2c data hold time 0 ?0 ? s t sudati2c data setup time 250 ?100 [11] ?ns t sustoi2c setup time for stop condition 4.0 ?0.6 ? s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? s t spi2c pulse width of spikes are suppressed by the input filter. ? ?050ns sda scl s sr s p t bufi2c t spi2c t hdstai2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c note 11. a fast-mode i2c-bus device can be used in a standard mode i2c-bus system, but the requirement t su;dat 250 ns must then be met. this automatically be the case if the device does not stretch the low period of the sc l signal. if such device does stretch the low period of the scl sig nal, it must output the next data bit to the sda line t rmax + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i2c-bus specification) befo re the scl line is released. [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. ** page 30 of 38 table 34. spi master ac specifications symbol description conditions min typ max units f sclk sclk clock frequency v dd 2.4v v dd < 2.4v 6 3 mhz dc sclk duty cycle 50 % t setup miso to sclk setup time v dd 2.4v v dd < 2.4v 60 100 ns t hold sclk to miso hold time 40 ns t out_val sclk to mosi valid time 40 ns t out_high mosi high time 40 ns table 35. spi slave ac specifications symbol description conditions min typ max units f sclk sclk clock frequency v dd 2.4v v dd < 2.4v 12 6 mhz t low sclk low time 41.67 ns t high sclk high time 41.67 ns t setup mosi to sclk setup time 30 ns t hold sclk to mosi hold time 50 ns t ss_miso ss high to miso valid 153 ns t sclk_miso sclk to miso valid 125 ns t ss_high ss high time 50 ns t ss_clk time from ss low to first sclk 2/sclk ns t clk_ss time from last sclk to ss high 2/sclk ns [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. ** page 31 of 38 packaging information this section illustrates the packaging specif ications for the cy8c20x36a /46a/66a/96a psoc device, along with the thermal imped- ances for each package. important note emulation tools may require a larger area on the target pcb than the chip?s footprint. for a detailed description of the emulation tools? dimensions, refer to the document titled psoc emulator pod dimensions at http://www.cypress. com/design/mr10161 . figure 15. 16-pin qfn no e-pad 3x3mm package outline (sawn) 001-09116 *d [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. ** page 32 of 38 figure 16. 24-pin (4x4 x 0.6 mm) qfn figure 17. 32-pin (5x5 x 0.6 mm) qfn 001-13937 *b 001-42168 *c [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. ** page 33 of 38 figure 18. 48-pin (300 mil) ssop figure 19. 48-pin (7x7 mm) qfn important notes for information on the preferred dimensions for mountin g qfn packages, see the following application note at http://www.amkor.com/products/n otes_papers/mlfappnote.pdf . pinned vias for thermal conduction are not required for the low power psoc device. 51-85061 *c 0.095 0.025 0.008 seating plane 0.420 0.088 .020 0.292 0.299 0.395 0.092 bsc 0.110 0.016 0.620 0.008 0.0135 0.630 dimensions in inches min. max. 0.040 0.024 0-8 gauge plane .010 1 24 25 48 0.004 0.005 0.010 [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. ** page 34 of 38 thermal impedances solder reflow peak temperature this table lists the minimum solder reflow p eak temperature to achieve good solderability. table 36. thermal impedances per package package typical ja [12] 16 qfn 32.69 o c/w 24 qfn [13] 20.90 o c/w 32 qfn [13] 19.51 o c/w 48 ssop 69 o c/w 48 qfn [13] 17.68 o c/w table 37. solder reflow peak temperature package minimum peak temperature [14] maximum peak temperature 16 qfn 240 o c 260 o c 24 qfn 240 o c 260 o c 32 qfn 240 o c 260 o c 48 ssop 220 o c 260 o c 48 qfn 240 o c 260 o c notes 12. t j = t a + power x ja . 13. to achieve the thermal impedance specifi ed for the qfn package, the center thermal pad must be soldered to the pcb ground pl ane. 14. higher temperatures may be required based on the solder melting point. typical temperatures for solder are 220 5 o c with sn-pb or 245 5 o c with sn-ag-cu paste. refer to the solder manufacturer specifications. [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. ** page 35 of 38 development tool selection software psoc designer? at the core of the psoc development software suite is psoc designer, used to generate psoc firmware applications. psoc designer is available free of charge at http://www.cypress.com/psocdesigner and includes a free c compiler. psoc programmer psoc programmer is flexible enough and is used on the bench in development and is also suitable for factory programming. psoc programmer works either as a standalone programming application or operates direct ly from psoc designer or psoc express. psoc programmer softwa re is compatible with both psoc ice cube in-circuit emulator and psoc miniprog. psoc programmer is available free of cost at http://www.cypress. com/psocprogrammer. development kits all development kits are sold at the cypress online store. cy3215-dk basic development kit the cy3215-dk is for prototyping and development with psoc designer. this kit supports in-circuit emulation and the software interface enables users to run, halt, and single step the processor and view the content of specific memory locations. psoc designer supports the advan ce emulation features also. the kit includes: psoc designer software cd ice-cube in-circuit emulator ice flex-pod for cy8c29x66a family cat-5 adapter mini-eval programming board 110 ~ 240v power supply, euro-plug adapter imagecraft c compiler (registration required) issp cable usb 2.0 cable and blue cat-5 cable 2 cy8c29466a-24pxi 28-pdip chip samples evaluation tools all evaluation tools are sold at the cypress online store. cy3210-miniprog1 the cy3210-miniprog1 kit enables the user to program psoc devices via the miniprog1 programming unit. the miniprog is a small, compact prototyping prog rammer that connects to the pc via a provided usb 2.0 cable. the kit includes: miniprog programming unit minieval socket programming and evaluation board 28-pin cy8c29466a-24pxi pdip psoc device sample 28-pin cy8c27443a-24pxi pdip psoc device sample psoc designer software cd getting started guide usb 2.0 cable cy3210-psoceval1 the cy3210-psoceval1 kit features an evaluation board and the miniprog1 programming unit. the evaluation board includes an lcd module, potentiomete r, leds, and plenty of bread- boarding space to meet all of your evaluation needs. the kit includes: evaluation board with lcd module miniprog programming unit 28-pin cy8c29466a-24pxi pdip psoc device sample (2) psoc designer software cd getting started guide usb 2.0 cable cy3214-psocevalusb the cy3214-psocevalusb evaluation kit features a development board for the cy8c24794a-24lfxi psoc device. special features of the board include both usb and capacitive sensing development and debugging support. this evaluation board also includes an lcd module, potentiometer, leds, an enunciator and plenty of bread b oarding space to meet all of your evaluation needs. the kit includes: psocevalusb board lcd module miniprog programming unit mini usb cable psoc designer and example projects cd getting started guide wire pack [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. ** page 36 of 38 device programmers all device programmers are purch ased from the cypress online store. cy3216 modular programmer the cy3216 modular programmer kit features a modular programmer and the miniprog1 programming unit. the modular programmer includes three programming module cards and supports multiple cypress products. the kit includes: modular programmer base three programming module cards miniprog programming unit psoc designer software cd getting started guide usb 2.0 cable cy3207issp in-system serial programmer (issp) the cy3207issp is a production programmer. it includes protection circuitry and an industrial case that is more robust than the miniprog in a production programming environment. note that cy3207issp needs s pecial software and is not compatible with psoc programmer. the kit includes: cy3207 programmer unit psoc issp software cd 110 ~ 240v power supply, euro-plug adapter usb 2.0 cable accessories (emula tion and programming) third-party tools several tools have been specially designed by the following thir d-party vendors to accompany psoc devices during development an d production. specific details for each of these tools can be found at http://www.cypress.com under documentation > evaluation boards. build a psoc emulator into your board for details on how to emulate your circuit before going to vo lume production using an on-chip debug (ocd) non-production psoc device, refer application note ?debugging - build a psoc emulator into your board - an2323? at http://www.cypre ss.com/?rid2748 . table 38. emulation and programming accessories part number pin package flex-pod kit [15] foot kit [16] adapter [17] CY8C20236A-24lkxi 16 qfn cy3250-20266qfn cy3250-16qfn-rk see note 15 cy8c20246a-24lkxi 16 qfn cy3250-20266qfn cy3250-16qfn-fk see note 17 cy8c20336a-24lqxi 24 qfn cy3250-20366qfn cy3250-24qfn-fk see note 15 cy8c20346a-24lqxi 24 qfn cy3250-20366qfn cy3250-24qfn-fk see note 17 cy8c20396a-24lqxi 24 qfn not available cy8c20436a-24lqxi 32 qfn cy3250-20466qfn cy3250-32qfn-rk see note 15 cy8c20446a-24lqxi 32 qfn cy3250-20466qfn cy3250-32qfn-fk see note 17 cy8c20466a-24lqxi 32 qfn cy3250-20466qfn cy3250-32qfn-fk see note 17 cy8c20496a-24lqxi 32 qfn not available cy8c20536a-24pvxi 48 ssop cy3250-20x66 cy3250-48ssop-fk see note 17 cy8c20546a-24pvxi 48 ssop cy3250-20x66 cy3250-48ssop-fk see note 17 cy8c20566a-24pvxi 48 ssop cy3250-20x66 cy3250-48ssop-fk see note 17 cy8c20636a-24ltxi 48 qfn cy3250-20666qfn cy3250-48qfn-fk see note 17 cy8c20646a-24ltxi 48 qfn cy3250-20666qfn cy3250-48qfn-fk see note 17 cy8c20666a-24ltxi 48 qfn cy3250-20666qfn cy3250-48qfn-fk see note 17 notes 15. flex-pod kit includes a practice flex-pod an d a practice pcb, in addition to two flex-pods. 16. foot kit includes surface mount feet that can be soldered to the target pcb. 17. programming adapter converts non-dip package to dip footprint. specific details and ordering information for each of the ada pters can be found at http://www.emulation.com . [+] feedback cy8c20x36a/46a/66a/96a document number: 001-54459 rev. ** page 37 of 38 ordering information the following table lists the cy8c20x36a/46a/66a/96a psoc devices' key package features and ordering codes. table 39. psoc device key features and ordering information package ordering code flash (bytes) sram (bytes) capsense blocks digital i/o pins analog inputs [18] xres pin usb 16-pin (3x3x0.6mm) qfn CY8C20236A-24lkxi 8k 1k 1 13 13 ye s no 16-pin (3x3x0.6mm) qfn (tape and reel) CY8C20236A-24lkxit 8k 1k 1 13 13 ye s no 16 pin (3x3 x 0.6 mm) qfn cy8c20246a-24lkxi 16k 2k 1 13 13 ye s no 16 pin (3x3 x 0.6 mm) qfn (tape and reel) cy8c20246a-24lkxit 16k 2k 1 13 13 ye s no 24-pin (4x4x0.6mm) qfn cy8c20336a-24lqxi 8k 1k 1 20 20 ye s no 24-pin (4x4x0.6mm) qfn (tape and reel) cy8c20336a-24lqxit 8k 1k 1 20 20 ye s no 24 pin (4x4 x 0.6 mm) qfn cy8c20346a-24lqxi 16k 2k 1 20 20 ye s no 24 pin (4x4 x 0.6 mm) qfn (tape and reel) cy8c20346a-24lqxit 16k 2k 1 20 20 ye s no 24-pin (4x4x0.6mm) qfn cy8c20396a-24lqxi 16k 2k 1 19 19 ye s yes 24-pin (4x4x0.6mm) qfn (tape and reel) cy8c20396a-24lqxit 16k 2k 1 19 19 ye s yes 32-pin (5x5x0.6mm) qfn cy8c20436a-24lqxi 8k 1k 1 28 28 ye s no 32-pin (5x5x0.6mm) qfn (tape and reel) cy8c20436a-24lqxit 8k 1k 1 28 28 ye s no 32 pin (5x5 x 0.6 mm) qfn cy8c20446a-24lqxi 16k 2k 1 28 28 ye s no 32 pin (5x5 x 0.6 mm) qfn (tape and reel) cy8c20446a-24lqxit 16k 2k 1 28 28 ye s no 32 pin (5x5 x 0.6 mm) qfn cy8c20466a-24lqxi 32k 2k 1 28 28 ye s no 32 pin (5x5 x 0.6 mm) qfn (tape and reel) cy8c20466a-24lqxit 32k 2k 1 28 28 ye s no 32 pin (5x5 x 0.6 mm) qfn cy8c20496a-24lqxi 16k 2k 1 25 25 ye s no 32 pin (5x5 x 0.6 mm) qfn (tape and reel) cy8c20496a-24lqxit 16k 2k 1 25 25 ye s no 48-pin ssop cy8c20536a-24pvxi 8k 1k 1 36 36 ye s no 48-pin ssop (tape and reel) cy8c20536a-24pvxit 8k 1k 1 36 36 ye s no 48-pin ssop cy8c20546a-24pvxi 16k 2k 1 36 36 ye s no 48-pin ssop (tape and reel) cy8c20546a-24pvxit 16k 2k 1 36 36 ye s no 48-pin ssop cy8c20566a-24pvxi 32k 2k 1 36 36 ye s no 48-pin ssop (tape and reel) cy8c20566a-24pvxit 32k 2k 1 36 36 ye s no 48 pin (7x7 mm) qfn cy8c20636a-24ltxi 8k 1k 1 36 36 ye s no 48 pin (7x7 mm) qfn (tape and reel) cy8c20636a-24ltxit 8k 1k 1 36 36 ye s no 48 pin (7x7 mm) qfn cy8c20646a-24ltxi 16k 2k 1 36 36 ye s yes 48 pin (7x7 mm) qfn (tape and reel) cy8c20646a-24ltxit 16k 2k 1 36 36 ye s yes 48 pin (7x7 mm) qfn cy8c20666a-24ltxi 32k 2k 1 36 36 ye s yes 48 pin (7x7 mm) qfn (tape and reel) cy8c20666a-24ltxit 32k 2k 1 36 36 ye s yes 48 pin (7x7 mm) qfn (ocd) [4] cy8c20066a-24ltxi 32k 2k 1 36 36 ye s yes notes 18. dual-function digital i/o pins also connect to the common analog mux. [+] feedback document number: 001-54459 rev. ** revised july 14, 2009 page 38 of 38 psoc designer? is a trademark and psoc? and capsense? are registered trademarks of cypress semiconductor corporation. all other trademarks or registered trademarks referenced herein are property of the respective corporations. purchase of i2c componen ts from cypress or one of its sublicensed associated companies conveys a license under the philips i2c patent rights to use these components in an i2c system, provided that the system conforms to the i2c standard specification as defined by philips. all pro ducts and company names mentioned in this document may be the trademarks of their respective holders. cy8c20x36a/46a/66a/96a ? cypress semiconductor corporation, 2009. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rig hts. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypres s. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a ma lfunction or failure may reasonably be expe cted to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com psoc solutions general psoc.cypress.com/solutions low power/low voltage psoc.cypress.com/low-power precision analog psoc.cypress.com/precision-analog lcd drive psoc.cypress.com/lcd-drive can 2.0b psoc.cypress.com/can usb psoc.cypress.com/usb document title: cy8c20x36a/46a/66a/96a capsense ? applications document number: 001-54459 revision ecn origin of change submission date description of change ** 2737924 snv 07/14/09 new silicon and document (revision **). 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